发明名称 DISPOSITIVO A CIRCUITO INTEGRATO A SEMICONDUTTORI.
摘要 In an MOS memory, a reference voltage is generated to determine an input threshold voltage of the input circuit. Noise fed from various signal wirings to the reference voltage wiring via stray capacitances is reduced by a decoupling capacitance formed between the reference voltage wiring and the ground wiring. The decoupling capacitance, however, permits relatively large levels of noise induced on the ground wiring by changes in the operation current of the circuit to be transmitted to the reference voltage wiring. According to this invention, a capacitance which forms a pair with the decoupling capacitance is provided between the power-supply wiring and the reference voltage wiring. Noise induced on the power-supply wiring by a change in the operation current of the circuit is substantially opposite in polarity to the noise induced on the ground wiring. Therefore, the noise fed from the ground wiring to the reference voltage wiring is cancelled by the capacitance provided between the power-supply wiring and the reference voltage wiring.
申请公布号 IT8124892(D0) 申请公布日期 1981.11.05
申请号 IT19810024892 申请日期 1981.11.05
申请人 HITACHI LTD 发明人 YOSHIAKI ONISHI
分类号 G11C11/419;G05F3/24;G11C5/06;G11C5/14;G11C11/401;H01L21/822;H01L23/522;H01L27/04;H01L27/06;H01L27/08;H03K17/16;H03K19/00;H03K19/0944;(IPC1-7):H01L/ 主分类号 G11C11/419
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