| 摘要 |
PURPOSE:To realize the operation of a balance type signal amplifying circuit by compensating the asymmetry of the capacity of bits, occurring on bit lines, to the symmetry of the element parameter of a sense circuit. CONSTITUTION:Firstly, when phi3 is at the high level, transistor (TR) Q11 is cut off during the operation of transfer gates Q7 and Q8, and an FF circuit is in operation by TRs Q2 and Q4. At this time, the ratio of beta2 and beta4 of those TRs is regarded as the ratio of bit capacities CB and C'B. In this case, however, mutual conductance gm of Q7 and Q8 is increased either by increasing betas of Q7 and Q8 or by holding phi3 very high. Next, as phi3 drops, signal amplification is performed only inside of FF operating by Q2 and Q4 and the unbalance between bit capacities CB and C'B is excluded by Q7 and Q8, so that balanced type FF will be preferable. For this purpose, beta11 and beta12 are so set that beta2+beta11=beta12+beta4 because Q13 turns on. Here, B is a common-emitter amplification factor and phi is a gate applied voltage. |
