Pulse generator for testing digital circuits - produces continually changing phase shift between clock pulse sequences using two counters

摘要

The pulse generator has two counters (Z1, Z2) receiving a basic clock signal (CK) and producing two output clock signals (ST, AT) reduced in frequency by a factor of 4 relative to the basic clock signal. In order to produce a continual phase shift in the two output clock signals, the second counter (Z2) is run independently of the first counter. Three JK flipflops (FF1, FF2, FF4) and one D-flipflop (FF3) are coupled to the counters to perform specified functions. The generator is intended for testing digital circuits and contains a small number of inexpensive components.