发明名称 FLIP-FLOP CIRCUIT
摘要 PURPOSE:To increase the reliability of FF by avoiding malfunction caused when noise is mixed to the input signal, by feeding back one and another output of the output signals of J-KFF to the input side and supplying each to each composite inversion logic circuit. CONSTITUTION:FF circuit 30 consists of the master FF10 and the slave FF20, and FF10 is constituted with AND gates 33, 37, OR gates 34, 38, and composite inversion logic circuits 36, 40 in series connection of NAND gates 35, 39. The output signal QM of this circuit 36 is inputted to the gate 38 of another circuit 40, and the output signal -QM of the circuit 40 is input to the gate 34. Further, FF20 is constituted with OR gates 5, 6 and NAND gates 7, 8, and they constitute the composite inversion ligic circuits 41, 42 respectively. Further, the output signals -QS, QS of the circuits 41, 42 are fed back to the input side of FF10 and fed to the gates 33, 39 via the NAND gates 31, 32 to avoid the malfunction due to mixing of input signal.
申请公布号 JPS56138322(A) 申请公布日期 1981.10.28
申请号 JP19800041543 申请日期 1980.03.31
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 HIRASAWA MASATAKA
分类号 H03K3/3562;H03K3/037 主分类号 H03K3/3562
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