| 摘要 |
PURPOSE:To enable to give an interpretation of instruction code and access to control memory in high speed, by giving the advanced-fetch instruction to the instruction word buffer and bypassing the instruction word buffer so that the instruction code of the instruction word branched can be stored in the instruction code register. CONSTITUTION:The instruction word arranging circuit 2 which positions the instruction code of the instruction word read out from the instruction word buffer 1 to be executed next to the upper most byte with the instruction word counter 7 and instruction word length detecting circuit 8, is provided. The write-in data to the buffer 1 and the instruction code output from the circuit 2 are selected at the instruction code selection circuit 3 with the branch detection circuit 9 of the instruction word during execution at present. Further, the output of the circuit 3 is set and the instruction code register 4 storing it is provided. Thus the branched advance fetch instruction is written in the buffer 1 and the instruction code only is bypassed to the instruction buffer through the circuit 3 to speed up the access to the control memory of the branched instruction word at branch. |
