| 摘要 |
There is provided a repair circuit including: a test data processing unit that outputs first and second defect detection signals in response to a test mode signal; a repair address control unit that receives addresses corresponding to a test target bank of a memory bank group in response to the first and second defect detection signals, sets a priority, and stores the addresses according to the scheduled priority; and a fuse unit that performs repair programming based on the addresses stored in the repair address control unit. Since defect address information is latched by the priority during a repair operation through a self-address rupture, repair operations for first and second sub-banks may be performed at the same time. |
