| 摘要 |
PURPOSE:To obtain a transistor bearable to a reverse bias at EB junction without an hFE deterioration phenomenon by avalanche break-down of the EB junction by a method wherein a side face of an emitter region is surrounded by an emitter region of low impurity concentration. CONSTITUTION:A P type silicon substrate 1 is formed with an N type first burried layer 2, a collector region 3-A, a P type second burried layer 4 and a P type separation region 5. Then, a P type impurity is implanted from the surface 3-A, a base region 9 being formed at the depth of the order of 1mu below the surface, and a P type region 8 for drawing out a base contact and the emitter region 10 being formed. The emitter region 10 is formed so as not to have a junction directly with the P type region 8 for drawing out the base contact. Since an N type epitaxial layer 3-a equivalent to the collector region exists on the side face of the emitter region 10, the hFE deterioration by recombination of the surfaces does not appear and accordingly, the EB withstand voltage is improved. |
