| 摘要 |
PURPOSE:To prevent the occurrence of a glitch securely by simple constitution, by making the rise time and fall time of a digital output signal coincide with each other by delaying the rise or fall. CONSTITUTION:If a digital signal outputted from digital output device 11 changes from [1, 0, 0...0] to [0, 1, 1...1] at some point, the most significant digit bit MSB changes from [1] to [0] and other bits change from [0] to [1]. While the other bits are still at level [0], MSB has fallen down to level [0], and glitch occurs temporarily to the output of device 11. On the other hand, MSB, while inverted by inverter circuit 12, is delayed and the delay time coincides with the rise time of the other bits. Then, the other bits rise without being delayed by inverter circuit 12, so that the both will coincide mutually. |
