| 摘要 |
PURPOSE:To perform real-time signal processing at a high speed and in bulk by arranging columns of processors and data buses by turns and by inputting data to the 1st processor column and obtaining outputs from processors at the final stage. CONSTITUTION:Processor columns of independent processors 10, 12...14 are arranged in the row direction. Then, processor columns are connected to each other by data buses 11, 13... which supply outputs of processors 10, 12...14 in one processor column to optional processors in the processor column of the next row. As a result, processor columns of processors 10, 12...14 and data buses 11, 13... alternate successively. Next, data is inputted to the processor 10 column and signal processing is performed in processor columns successively to obtain output data the processor 14 column at the final stage. Thus, the read-time signal processing is performed at a high speed and in bulk. |
