| 摘要 |
A signal processing circuit divides a digitized video signal of each horizontal scan interval into a plurality of data blocks D1 to D8, and a signal distributing circuit distributes the data blocks D1 to D8 within each horizontal scan interval between rotary magnetic heads in a helical scan VTR. For each horizontal interval, heads GA, GB, GC, GD (Figure 8 not shown) simultaneously record blocks D1, D3, D2, D4 respectively then blocks D5, D7, D6, D8 respectively. The heads are stacked, together with an audio head AH, with a slight circumferential stagger and delay circuits may be used so that the ends of the tracks are effectively aligned in the track width direction or staggered in the track length direction each field being recorded as a set of four digital, video tracks and one digital audio track (Figures 9, 11, not shown). Each data block D1 to D8 includes a sync signal, track identification and address signals and block parity data (Figure 4H). In the video recording circuits, Figure 2 (not shown), an interface (11) halves the data rate and multiplexes the data blocked to an AB channel and a CD channel. Each such channel has a time base compression circuit (12), to make room for error codes, an error correcting encoder (13), and a recording processor (14) which converts from 8 to 10 - bits per sample and feeds record amplifiers for two heads (GA and GB, or GC and GD). In the audio recording circuits, (Figure 6 not shown), 16 analog signals are converted to digital form then multiplexed onto one audio recording channel which includes a time compressor (75), and an error correcting encoder (76). On reproduction, an analyzer ANA indicates the number of data blocks having errors on a monitor 6, (Figures 1, 10 not shown). <IMAGE> |
