| 摘要 |
PURPOSE:To check the normalcy of address conversion highly efficiently by a small number of bits, by checking the normalcy of the correspondence relation between logical addresses and actual addresses on the basis of flag bits. CONSTITUTION:Corresponding to logical address 10, actual address register 7 is controlled via logical address register 6, comparing circuit 8, etc., to generate flag bit 11 on the basis of exclusive OR between the corresponding actual address and the address-conversion-objective AU part added to the address. This bit 11 is compared by comparator 13 with the flag bit, generated by flag-bit generator 12 by exclusively ORing bit 11 and the actual bit, to judge the propriety of address conversion according to their coincidence and dissidence. Therefore, the normalcy of the correspondence between the logical address and actual address can be checked highly efficiently by a small number of bits without using the bit equal in length to the logical address. |
