| 摘要 |
PURPOSE:To provide a small-sized Si gate FET by a method wherein a front surface and side surfaces of gate electrode are covered by PSG (having P of 5mol% or more) and a resistant interconnect structure of source and drain arranged in a gate electrode is exposed in the gate electrode under its self-alignment. CONSTITUTION:Opening is made in SiO2 2 on P type base plate 1, and then SiO2 thin film 3, N type poly-Si 4, and PSG5 are overlapped with each other. The films 5, 4 are etched in sequence with a resist mask 6 to form films 7, 8. Opening is made in the film 3 with the mask 8, some ions are implanted in the exposed base plate surface to form N type source 11 and drain 12. Then, they are processed in N2 at 1,000 deg.C, PSG7 is softened to cover the front and side surfaces of poly-Si 8. Opening is made at 17 in PSG7 on the gate electrode 8 and then A1 interconnect structures 13-15 are arranged. With this arrangement, the interconnect structure of source and drain of the insulation gate FET may be formed at the gate electrode under its self-alignment, so that a shape of the source and drain may be reduced and a high speed operation in the element may be assured. |
