| 摘要 |
<p>Solid stage apparatus for the detection of synchronism between line and bus voltages in order to permit safer interconnection therebetween is disclosed. A first comparator circuit constantly monitors the magnitude of the vector difference between the line voltage and the bus voltage and generates a first enabling signal whenever the magnitude of the vector difference voltage is below a predetermined value. The first enabling signal will continue to be generated until the magnitude of the vector difference voltage rises above the predetermined value. A second comparator circuit monitors the relative magnitudes of the line and bus voltages and generates a second enabling signal whenever a high bus-dead line or a dead bus-high line circuit occurs. The second enabling signal will continue to be generated as long as one of these conditions exist. The enabling signals are applied to a time delay circuit. If either enabling signal is applied to the time delay circuit for a predetermined time period, the time delay circuit will generate an output signal which enables a connection between the bus and line.</p> |
