发明名称 TELEVISION RECEIVER
摘要 PURPOSE:To use the small-capacity and low-speed picture memory block to display one picture large, by writing picture signals of respective parts of the TV picture corresponding to one-screen components in plural picture memory blocks. CONSTITUTION:Picture signals received by one receiving circuit 2a are applied to picture memory blocks 1a-1d commonly, and write controllers 6a-6d are controlled by the clock signal from one write clock generating circuit 7a. Timings when respective parts are written in blocks 1a-1d are set by controllers 6a-6d. For example, when the control signal is input from terminal 14, signals of the first half and the latter half of one field and the first half and the latter half of one line are output and written by controlling controllers 5a-5d. Picture signals are read out continuously from blocks 1a-1d successively to display one picture large.
申请公布号 JPS56132066(A) 申请公布日期 1981.10.16
申请号 JP19800035317 申请日期 1980.03.19
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 FUJITA MASAAKI;UEDA MINORU;KAWASHIMA KAZUMI;YAMAMOTO HIROSUKE;TAIRA HIDEKAZU
分类号 H04N5/45;(IPC1-7):04N5/44 主分类号 H04N5/45
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