| 摘要 |
<p>A control architecture is disclosed for a communications controller, for connecting a control processor (32) in the communications controller to a plurality of internal processing subunits (50 - 300) which operate asynchronously at different data rates. The architecture includes a control adapter (500) which is connected between the control processor and a common subunit bus (604), for receiving from the control processor, a control command, a plurality of data words, and an associated address for a respective one of the processing subunits. The control adapter outputs an operating code and the plurality of data words on the common subunit bus and further outputs a subunit select signal on a respective subunit select line to the subunit designated in the address. The adapter further includes a memory for storing the number of shift intervals to be applied to a stack shift signal which is output on a stack shift bus which is common to all of the subunits. The architecture further includes a register stack in each of the processing subunits. having a data input connected to the common subunit bus and a select input connected to the respective subunit select lines from the adapter. Each selected register stack will serially shift and store the operating code and each of the plurality of data words from the common bus, into respective stages of the register stack. The control architecture further includes a timer and a response time storage in the control adapter, having a stored, predetermined execution period associated with each of the processing subunits so that data can be selectively read from each of the subunits without regard for its asynchronous operation.</p> |
