发明名称 MULTIPROGRAMMED DATA PROCESSING SYSTEM WITH IMPROVED INTERLOCK CONTROL
摘要 <p>A MULTIPROGRAMMED DATA PROCESSING SYSTEM WITH IMPROVED INTERLOCK CONTROL A multiprogrammed data processing system with reduced processing time for interlock instructions compares the first partial address contained in a request with a corresponding first partial address of an interlocked address in a first comparator when a main storage control unit receives the request from one of central processing units. The main storage control unit sends the request to a main memory in response to a non-coincidence signal from the first comparator. In response to a coincidence signal from the first comparator the main storage control unit compares a second partial address contained in the request with a corresponding second partial address of the interlocked address. The main storage control unit sends the request in response to a non-coincidence signal from the second comparator.</p>
申请公布号 CA1110725(A) 申请公布日期 1981.10.13
申请号 CA19780313345 申请日期 1978.10.13
申请人 HITACHI, LTD. 发明人 SHIMIZU, TSUGUO;MATSUURA, TSUGUO
分类号 G06F12/00;G06F9/46;G06F9/48;G06F15/16;G06F15/177;(IPC1-7):06F15/16 主分类号 G06F12/00
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