| 摘要 |
PURPOSE:To enable to synchronize even with fading and burst, by transmitting signal series including the start point of data plural times. CONSTITUTION:The address from CPU1 is read out from the address decoder 2, control data is from RAM8 and each pattern is read out from ROM9. This is input from the output teminals D0-D7 to the latch circuit 4 with sectioning and it is latched with the clock from the address decoder 2. The length of data sectioned is input from the output terminals D0-D3 of CPU1 to the latch circuit 6, it is latched with the clock from the address decoder 2 and set to the counter 7. The output DS counted in external timing ST is transmitted, and carry signal CRT interrupts CPU1 at the end of count of the set value and the next data is output. Thus, the data start point can accurately be detected even with fading and burst noise. |
