| 摘要 |
<p>A semiconductor memory device comprises a plurality of memory blocks (MB) each including a sense amplifier array (SAG) and a pair of memory cell groups (CG) disposed on opposite side of the sense amplifier array. A row decoder (RD) selects a row line (RL) in the memory blocks. Pairs of bus lines (BUS) are provided, each pair corresponding to one of the sense amplifier arrays. A column decoder (CD) is common to the plurality of memory blocks and selectively connects a pair of input/output terminals of a sense amplifier of the sense amplifier array (SAG) in each of the memory blocks (MB) to a corresponding one of the pairs of bus lines (BUS).</p> |
