| 摘要 |
PURPOSE:To obtain a high-speed characteristic by means of a simple circuit configuration, by correcting so that a frequency dividing circuit outputs a data which is equal to a frequency dividing value data, in case when an output data of the frequency dividing circuit to which the frequency dividing data is provided is different from the frequency dividing data. CONSTITUTION:In case when the frequency dividing circuits 20-80 of the second stage and thereafter are set to a state ''1'', when the output of the inverter 33 is in ''1'' level, that is to say, when it is inhibited to input a preset data, an input signal which rises to ''1'' level is applied to the frequency dividing circuit 20. When a state of the frequency divider is 10,000,000, the output of the inverter 33 becomes ''0'' level, therefore, when a preset signal is inputted at that time, the contents of only a counter in which a preset data is positioned at ''0'' are corrected to ''0'', and as a result, a normal preset data N value is set. In this way, since only a frequency dividing circuit which is in a down-counted state is corrected, a high speed characteristic can be obtained. |
