| 摘要 |
A fast, parallel operating device for multiplying binary coded numbers. The numbers are divided into groups of n bits of directly successive significance levels. Subsequently, all feasible combinations of one group of the first number and one group of the second number are formed, for each combination a partial product being formed in a first array of partial product forming devices. A partial product is preferably formed by a logic circuit which operates non-sequentially but exclusively combinatory, and which has a logical depth of only three gates. The partial products are subsequently applied to a second array of partial sum forming devices in which they are added together with intermediate partial sums, taking into account their relative significance levels. Together with the partial product digit of lowest significance, the final row of partial sum forming devices then generates, co-operating in parallel, the complete product. A corresponding method can be used for the multiplication of binary numbers in two's complement representation. In that case the product of the parts after the decimal point must be increased by the cross products of the parts before the decimal point and the inverted values of the parts of the two numbers after the decimal point. The part of the product before the decimal point is obtained by modulo-2 addition of the parts before the decimal point of the two number in two's complement representation itself.
|
