| 摘要 |
PURPOSE:To obtain an output of integration that is free from a stray capacity, by providing a switch which performs a control with the fist phase clock plus a switch which performs a control with the second phase clock centering on the sampling capacitor. CONSTITUTION:The analog switches 33 and 34 which work with the first phase complementary clock phi1 plus the switches 31 and 32 which work with the second phase complementary clock phi2 having a different phase due to the polarity of the output to be obtained are distributed centering on the sampling capacitor 14. As shown in the input clock time chart, both of the clocks phi1 and phi2 are set at the same high or low level with the necessary switch turned on. Thus the output phase has the opposite polarity; while the clocks phi1 and phi2 are set the opposite level of the high or low level with the switch turned on to obtain the same polarity for the output signal. In such way, an integral output signal can be obtained with no effect of a stray capacity in both cases mentioned above. |
