| 摘要 |
PURPOSE:To obtain stable block synchronism and to enable to transmit two systems of information with good efficiency, by transmitting the 2nd information through the conversion into a code form absent in di-pulse and the conversion of the 1st information into di-pulse. CONSTITUTION:Clock pulse CLK1 in 2f0 is fed to each clock terminal C of FFs 1,2,input signal DPLS is fed to the data terminal D of FF1, FFs 1, 2 are operated as shift register, and the output of terminal Q of FF2 is fed to the data terminal D of FF6. A 1/2 frequency-divider 4 adds CLK1 inverted at the inverter 9 to the clock terminal C and outputs the clock pulse CLK2 of frequency division output from the terminal Q. CLK2 is fed to the clock terminal C of FFs 6, 8. The code detection gate 4 inputs the output of each terminal Q of FFs 1, 2 and CLK1 inverted with the inverter 9, and when both are ''1'', the output is made to ''0'' and it is fed to the reset terminal R of the 1/2 frequency-divider 4 for reset. |
