发明名称 PROCESSING DELAY SYSTEM
摘要 PURPOSE:To surely verify the normality of action in logical function parts by previously integrating a function which intentionally delays the execution of processing into a device, activating the function at the time of a test, and consciously setting an environmental condition in the device and other devices connected to the device as if they are highly loaded. CONSTITUTION:The means for intentionally delaying the processing is previously integrated into the device executing the prescribed processing with taking much time. Furthermore, a means for designating whether or not to delay the processing is provided, and normally the means is caused to execute the processing without intentional delay, and is caused to operate with intentional delay at the time of the test. A means for designating the range of delay time (upper bound, lower bound) and a means for changing the delay time within the range are provided, whereby the delay of respective lengths is added within the range. Since the logical function parts operating under special condition can be operated, the normality of the functions can effectively be verified.
申请公布号 JPS63311540(A) 申请公布日期 1988.12.20
申请号 JP19870147058 申请日期 1987.06.15
申请人 HITACHI LTD 发明人 MORIKAWA TAKASHI;SATO KIICHI
分类号 G06F11/22 主分类号 G06F11/22
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