发明名称 SYNCHRONIZATION CONTROLLING SYSTEM MICROPROCESSOR PERIPHERAL CIRCUIT
摘要 <p>PURPOSE:To process data transfer at the highest speed of a CPU under the condition at all times, by switching the cycle of the clock for driving a microprocessor in accordance with the responding speed of individual memories or input/output (I/O) devices to which the data transfer is an object. CONSTITUTION:A clock switching means 3 which changes the cycle of a clock for driving a microprocessor 1 in accordance with the responding speed of a memory or one of I/O devices 11A and 11B is provided and a code is inputted from a code selecting means 4 to control the clock switching means 3. Namely, when the microprocessor 1 makes operations, the block is frequency-divided by means of the means 3 so that the microprocessor 1 can operate at its original operation executing speed and, when data transfer is made to a memory or one of the I/O devices 11A and 11B, the code selecting means 4 is controlled by means of a detection signal from read and write signals so that the CPU 1 can operate in a transfer time having no useless waiting time in accordance with the responding speed of the data to be transferred. Therefore, the memory or I/O devices 11A and 11B can make access at the highest speed as much as possible.</p>
申请公布号 JPS63311554(A) 申请公布日期 1988.12.20
申请号 JP19870148689 申请日期 1987.06.15
申请人 MITSUBISHI ELECTRIC CORP 发明人 KAWAI JOJI
分类号 G06F1/06;G06F1/08;G06F13/42;G06F15/78 主分类号 G06F1/06
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