IGFET Decode circuit using series-coupled transistors

摘要

A decoder circuit suitable for integrated circuit implementation using IGFET processing is disclosed which may be implemented in a highly dense structure. The decoder output lines are grouped in pairs and at least one of the output lines in each pair is discharged as determined by a bit in the input address. A plurality of IGFET devices under the control of the remaining input address bits selectively couple together the two output lines in each pair such that both output lines can then become discharged. Series-coupled pairs of IGFET devices are used in place of a single IGFET device in order to reduce the chip area required to implement the decoder structure.