| 摘要 |
A static Random-Access-Memory having a single bit line between each pair of adjacent columns of memory cells, implemented in a self-aligned, N-channel, silicon-gate system. Resistor element load devices are made in second-level polycrystalline silicon by an ion implant step. The second-level polycrystalline silicon is insulated from the first-level polycrystalline silicon by a multiple oxide insulation layer. An additional word line for each row of memory cells provides differentiation between adjacent memory cells sharing a single bit line. |
