发明名称 HIGHHSPEED DATA TRANSFER SYSTEM BETWEEN PROCESSORS
摘要 PURPOSE:To make data transfer in high-speed, by selecting whether data should be caused to pass through the processor block or bypass it according to the state of processors in this processor block for data transfer. CONSTITUTION:When, for example, three processors 11 in the processor block are in the data through state, that is, when all processors 11 in the processor block do not inhibit by-passing of data, this state is reported to selector control circuit 14. Selector control circuit 14 connects selector 12 to the by-pass 13 side to by-pass this processor block. Consequently, data transfer between processors can be performed in high-speed, and the number of connection lines between processors is reduced.
申请公布号 JPS56123053(A) 申请公布日期 1981.09.26
申请号 JP19800027623 申请日期 1980.03.04
申请人 NIPPON TELEGRAPH & TELEPHONE 发明人 KONDOU TOSHIO;AOKI MAKOTO;NAKASHIMA TAKATOSHI
分类号 G06F13/38;G06F15/16;G06F15/173;G06F15/80 主分类号 G06F13/38
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