| 摘要 |
PURPOSE:To execute the operation test and debug of each I/O equipment by means of a simple operation, by installing a debug console memory having other space memory than the equipment controller memory connected with the bus. CONSTITUTION:In case when the firmware ROM21 is debugged, the memory contents of the ROM21 are loaded in advance in the RAM61 of the debug console 5, or the ROM21 is changed for the place of the RAM61. After that, when an inhibit signal is sent to the I/O equipment controller 1 through the cable 7, the work memory RAM22 and the RAM61 are formed in one body. In this state, the ROM21 can be debugged. Subsequently, in case of executing the test operation of the I/O equipment, a program from the external memory device 8 is written in the RAM61. After that, the RAM61 and the RAM22 are formed in one body by sending an inhibit signal to the controller 1. The controller 1 is operated by reading out a test data from the memory which has been formed in one body. In this way, the I/O equipment can be tested. |
