| 摘要 |
PURPOSE:To increase accuracy of discrimination, by detecting the VTR output at a variable speed playback mode, through the use of the number of counts of pulses during composite synchronizing signals present for the specified period from the time point detecting consecutive pulse for 0.4 horizontal period or more. CONSTITUTION:Clock pulse CP from a clock oscillator 1 is fed to a frequency division counter 2, becomes an internal vertical synchronizing signal Pv0 and is fed to vertical drive circuit 3. Further, the external vertical synchronizing signal P1 separated with the separation circuit 6 from the composite synchronizing signal COMP.S is fed to reset pulse forming circuits 7, 8 to result the 1st and 2nd reset pulses PR1, PR2 and fed to the selection circuit 9. Further, the discrimination circuit 10 discriminates if the number of pulses preset in the specified period from the time point detecting pulses to be consecutive for 0.4 horizontal period of the composite sychronizing signal COMP.S or more and the selection circuit 9 is switched with the output of discrimination. |
