| 摘要 |
Synchronizing the phase of a locally generated clock signal with the phase of an input signal is usually effected by using a phase-locked loop, but this has a drawback that a certain run-in time is necessary to be sure that the phase of the clock signal is stable. The present arrangement comprises a delay line (2) having taps (3), the delay line being driven by a crystal oscillator 1. Clock signal versions C1(0), C1(90), C1(180) and C1(270) which are phase shifted relative to one another through 90 DEG available at the successive taps (3). A coincidence detection circuit comprising trigger circuits (9) and a combining network (10) detects the version of the clock signal whose ascending edge, for example, is located nearest to an ascending edge of the data signal, and this version is supplied as the clock signal at an output (8) by the selective control of switches (7) by control signals from the outputs (13) of the network (10). |
