| 摘要 |
PURPOSE:To enable to halve the number of multipliers of a delay equalizer, by making the difference and the sum between the signal input from the input terminal of a filter and the signal fed back from the output terminal via a delay element, multiplying the coefficient of transfer function to each output and adding the output of the difference to the sum of output via a delay element. CONSTITUTION:The signal input from an input terminal 201 and the signal fed back through a delay element 205 from a filter output terminal 202, are added and substracted at adders 204 and 203 respectively, and they are multiplied with the coefficient of the transfer function at multipliers 211-214, and the output of the multipliers 211 and 213 is respectively subtracted and added at adders 224 and 221. Further, the input signal is input to the adder 224 via a delay element 234, the output of addition is fed to the adder 221 via the adder and delay element at the next stage, and the output of the digital delay equalizer is obtained from the output of the adder 221. |
