| 摘要 |
PURPOSE:To prevent the variance of phase of output sampling clock, by frequency division of 1/(N-), 1/(N+1), and 1/N of the output signal of an oscillator according to the ternary output of lag, lead of phase comparator, and absence of phase information, respectively. CONSTITUTION:When an output of a termary phase comparator 101 is lead, since the preset value of the frequency divider 103 is set to 129 with the preset value logic circuit 104 and set to 128 when lagging, the frequency divider 103 frequency-divides the output of the fixed frequency oscillator 102 into 1/127, 1/129 and 1/128 respectively. Thus, the output phase leads by about 1/128, and lags by about 1/128 and changes in phase in said direction, every about 1/128 frequency division. Thus, the clock in phase matching with the equalized wave input 10 at the output terminal 20 at >=+ or -1/128 error at all times, can be obtained. |
