| 摘要 |
PURPOSE:To obtain an amplitude limiting circuit which is easy to mount on the semiconductor integrated circuit, by connecting commonly sources of N channel and P channel FETs and by connecting drains to the power source and the earth respectively and by giving a reference voltage to gates. CONSTITUTION:The input signal from terminal 7 is output to terminal 10 through amplifying circuit 8 and resistance 9. Terminal 10 is connected to sources of N channel (CH) FET11 and P (CH) FET12 which are connected commonly, and drains of FETs 11 and 12 are connected to power source terminal 13 and the earth respectively. Resistances 14-17 are connected between terminal 13 and the earth, and the connection point between resistances 16 and 17 and the connection point between resistances 14 and 15 are connected to gates of FETs 11 and 12 respectively. Voltages at both ends of resistances 15 and 16 and pinch-off voltages of FETs 11 and 12 are denoted as E15, E16, EP11 and EP12, respectively; and when voltage 10 of terminal 10 becomes E18+EP12+E15 or more with voltage E18 of connection point 18 between resistances 15 and 16 as the reference, FET12 is turned on to limit the rise of voltage 10. When voltage 10 becomes E18-(EP11+E16) or less, FET11 is turned on to limit the fall of voltage 10. |
