| 摘要 |
PURPOSE:To eliminate jitter of the demodulating carrier signal, by converting the output signal of the intermediate frequency IF amplifier to an amplitude modulation signal and by inputting this signal to the PLL circuit and by inputting the output signal of the PLL circuit and the output signal of the IF amplifier to the multiplying circuit. CONSTITUTION:The signal of IF amplifying circuit 3 is supplied to one input terminals of adding circuit 8 and mixing circuit 9. At this time, if PLL circuit 5 consisting of phase comparing circuit 5a, LPF5b, voltage control oscillator 5d, and 1/2 frequency divider 11 is locked, the output signal of oscillator 5d is mixed with the output signal of circuit 3 by circuit 9, and the output signal and the output signal of circuit 3 are added by circuit 8, and the result is input to BPF10. The amplitude modulation signal is always obtained in the output of BPF10, and this signal is compared with the output signal of frequency divider 11 by phase comparing circuit 5a and passes through LPF5b, and thus, low-frequency components which performs angle modulation of oscillator 5d are not generated in the output of LPF5b. The output of frequency divider 11 is input to multiplier 4 through 90 phase shifter 6 and is multiplied by the output of circuit 3, thereby reducing jitter to obtain a good demodulation signal at terminal 7. |
