| 摘要 |
A delay lock loop comprises: a first input (12) receiving a first input pulse train; a pulse edge detector (22) for receiving at a first input the first input pulse train and for producing an output signal related to the time interval between an edge transition of a pulse on the first input and a second input of said edge detector; a second input (14) receiving a second input pulse train; a variable delay (26) connected to the second input for providing a variable delay output pulse train with respect to the second input pulse train; and a feedback (44, 55) for producing a feedback signal from the output signal of the edge detector to provide an input to the variable delay to control the output thereof; a delayed output of the variable delay being connected to the second input of the edge detector. The delay lock loop may be applied, for example, to a self-adjusting phase equaliser, a self-adjusting delay device, a single or dual input frequency dependent demodulator, or a modulator/demodulator. <IMAGE> |
