| 摘要 |
PURPOSE:To prevent erroneous operations and lower electric power consumption in a memory device consisting of a pair of driver FET and a cell having load resistance, by switching current in a pair of bit line between the power source and the cell and flowing a great amount of current when selected. CONSTITUTION:Depression (D) type FETs Q1d, Q'1d are mounted to the bit line BL1 and barred BL1 and a row selection signal Y1 is input. Likewise Qnd, Q'nd are mounted to the bit line BLn and barred BLn and a signal Yn is input. These d type FET are not in complete ''off'' state even when the signal in ''L'' and minimum enough currents flow to prevent any erroneous operation. And because the bit lines maintain stable positions, erroneous operations and lowering of operation speed can be prevented. To the nonselective cell commonly connected to the word line to which such selective memory cells CEL are connected, only weaker currents flow than one from load FET. Therefore electric power consumption as a whole is lowered. |
