| 摘要 |
<p>Disclosed is a time division multiplex system in which frame synchronization requires a low transmitting capacity and a high synchronizing security on the one hand and a rapid reaction to synchronization interferences on the other hand. According to this invention, two synchronized words, each comprising at least six synchronizing bits, are decoded and one synchronized bit each per frame is transmitted in the multiplex signal. Upon recognition of the two synchronized words, a counter is reset in the unsynchronized state, by which counter a synchronizing signal is produced for controlling an address pick-up. The synchronizing is monitored by means of one synchronizing word.</p> |
