| 发明名称 |
Electrical validator for a printed circuit board test fixture and a method of validation thereof |
| 摘要 |
This invention relates to a structure for testing the integrity of a printed circuit board test fixture and to a method for implementing the verification of the fixture.
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| 申请公布号 |
US4290015(A) |
申请公布日期 |
1981.09.15 |
| 申请号 |
US19790086220 |
申请日期 |
1979.10.18 |
| 申请人 |
FAIRCHILD CAMERA & INSTRUMENT CORP. |
发明人 |
LABRIOLA, DONALD J. |
| 分类号 |
G01R31/02;G01R1/073;G01R31/28;(IPC1-7):G01R31/00 |
主分类号 |
G01R31/02 |
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