| 摘要 |
Effective expansion of a common intermediate buffer memory by equivalent use of the buffer memory in each CPU in a multiprocessor system. A method and system for achieving buffer memory coincidence is applied to a multiprocessor system provided with central processing units, buffer memories contained in respective central processing units, a main memory, and an intermediate buffer memory connected between the main memory and the buffer memories, wherein a buffer invalidation address information (BIA GO) is sent from the intermediate buffer memory to the i-th central processing unit (BIA GO #i) in accordance with the following logical expression: BIA GO #i=REQ.CPUxWx{F upsilon Fx(COPY#i upsilon VIF)} where the term "REQ.CPU" indicates that the i-th central processing unit does not provide a request for accessing the intermediate buffer memory, the term "W" indicates that the above request is a request for writing a data block, term "F" and "F" indicate that the accessed data block is found and is not found, respectively, in the intermediate buffer memory, the term "COPY #i" indicates that a copy of the corresponding data block is stored in the buffer memory of the i-th central processing unit, the validity flag term VIF indicates the possibility that the copy flags are incorrect, and the symbols "x" and " upsilon " represent a logical product and a logical sum, respectively. This method makes it possible to store data blocks which exist only in the buffer memory but do not exist in the intermediate buffer memory.
|
