| 摘要 |
PURPOSE:To reduce the processing time, by adding the display bit during data transfer to the address array and providing the address word/address stacker of pushup store. CONSTITUTION:To address array 2, in addition to the effectiveness display bit V, the bit T displaying that the readout request data is under transferring from the main memory device is added. Further, the column address word address stacker 7 of FIFO system storing the column address and word address, and the comparator 9 are provided. Further, by controlling these at the control section 5, a plurality of processing requests from the processor are sequentially received for parallel processing, resulting that the waiting time is decreased and the processing time can be reduced. |
