| 摘要 |
PURPOSE:To simplify the circuit, by providing a pull-up resistor between the output of series MISFET of the prestage and the voltage terminal and forming the start signal at the application of power supply, in a ring counter consisting of MISFETs. CONSTITUTION:While the first clock pulse phi1 is fed after the application of the power supply, the gate of an MISFETQ4 is charged up to the on-level through an MISFETQ7 provided between the output of series MISFETs Q1, Q2 of the prestage circuit and the voltage terminal VDD, then the output A is formed in synchronizing with the clock pulse phi1. With the leading of the output A, MISFETQ2' of the next stage is on, the gate of MISFETQ4' is charged up to form the output B with the first clock pulse phi2, and MISFETQ6 of the prestage is on to make reset. Similarly, outputs C-H are output, the first stage circuit is set with the output H of the final stage, allowing the operation of ring counter. |
