| 摘要 |
PURPOSE:To enable the constitution of digital circuit, to make ease of adjustment and to make stable the operation, by detecting asynchronous state between the reference signal and the comparison signal, when the value counting the frequency difference between the reference signal and the comparison signal reaches a given value. CONSTITUTION:In the asynchronous state of frequency fR of the reference signal < frequency fV of comparison signal, the subtraction by comparison pulse (d) is repeated, and when count outputs QA-QC show a given value 2, FF1 is set and the formation of the reference pulse (c) and compared pulse (d) is blocked, and output is made by taking the output (n) of FF3 as the synchronous detection output OUT2. In the asynchronous state of fR>fV, the addition of the reference pulse (c) is repeated, and when the count outputs QA-QC reach a given value 6, the reference pulse (c) and the comparison pulse (d), and the output (m) of FF2 is output as the synchronous detection output OUT1. Thus, the change of the frequency of comparison signal in comparison with the frequency of the reference signal can be detected. |
