发明名称 CIRCUIT CHECK SYSTEM FOR INFORMATION PROCESSOR
摘要 PURPOSE:To reduce a test time, by rejecting the duplicated steps of a software check by program logic array. CONSTITUTION:The software is assembled by writing in instructions in ROM12. The address decoder 13 is connected to the rows of ROM12 and the information 14 from the counter 18 is input to the address decoder 13. Further, the column decoder 15 is connected to the column lines of ROM12. The latch 16 is connected to the column decoder 15 and the instruction decoder 17 is connected to the latch output. Further, the control circuit 19 is connected to the counter 18 and the input circuit 20 and various data signals are connected to the control circuit 19. To the input circuit 20, the input signal RCH from the check terminal 21, jump signal JP from the instruction decoder 17, subroutine call signal SC and subroutine return signal SR are fed.
申请公布号 JPS56116156(A) 申请公布日期 1981.09.11
申请号 JP19800019198 申请日期 1980.02.20
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 SUEDA AKIHIRO;KINUGASA MASANORI;HIRAI SEIICHI
分类号 G06F11/22;G06F11/273 主分类号 G06F11/22
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