Demodulator for frequency shift data transmission - has zero crossing detector and accumulators to count signal over given time period

摘要

The output of the detector (1) is fed to a delay network (2) and also to a converter (3) which provides a numerical value for the number of detected zero crossings. The delayed output (2) is also fed to a converter (4) that also provides a numerical value for the detected zero crossings. Both values from the converters (3,4) are clocked into an adder (5) by an internal clock pulse generator. The output of the first converter (3) is also fed to an accumulator (6) driven by a control circuit (7) which determines the measurement time period. The output of the accumulator (6) is used for comparison with the adder output accumulator (8) over the same given time period, the first accumulator being read into the second (8) by the clock, so that the comparator (9) can output a value according to whether the input was over or under the mid-frequency, or carrier.