Digital measuring signal timing circuit - has recognition circuit connected by gate switch to frequency divider controlled by stopping pulses and counter

摘要

The timing system for digital signals obtained from a measuring pulse pattern includes a recognition circuit connected to a frequency divider driven by a preset counter operating through a gate switch. This is controlled by bits controlled by clock pulses, the divider ratio corresponding to the quotients of the bit cycle, and the measuring cycle. The output of the frequency divider is connected to a multiple unit separator which gives a switching pulse when a stop pulse is received from the recognition circuit during each cycle. The recognition circuit is connected to another input of the separator, whose output is connected to the gate switch. The output of the gate switch is also returned to the setting input of the separator. The output of the frequency divider is connected to a control input of a switch which is also connected to a starting pulse transmitter and which is connected to the source of the measuring pulses, and to a counter.