发明名称 MANUFACTURE OF MIS FIELD EFFECT TRANSISTOR INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To reduce the size of the entire integrated circuit device by forming a source electrode, a wire layer and a drain electrode, a wire layer without using a mask layer for forming a window connected to the source and drain regions, thereby reducing the size of the window. CONSTITUTION:An element isolating insulating layer 6 is formed on the main surface of the semiconductor substrate 1, and the insulating layer 6 and a thin insulating layer 01 are formed thereon. A conductive layer C1 is formed by an accumulation process, a mask layer M1 is formed, and a conductive layer C2' is formed by etching. With the layers M1, C2' as masks the layer 01 is etched to form a gate insulating layer 9, and regions Z1, Z2 with an element forming region 5 are exposed. Thereafter, a mask M2 is formed by an accumulation process, and the layer C2' sidewisely etched is removed. With the mask M3 as a mask the layer C2' is oxidized thermally to form gate electrode 8 and interlayer insulating layer 32 on the layer C2'. The layer M3 is etched to expose the layers Z1, Z2, and windows H1, H2 are formed.
申请公布号 JPS56115569(A) 申请公布日期 1981.09.10
申请号 JP19800018722 申请日期 1980.02.18
申请人 NIPPON TELEGRAPH & TELEPHONE 发明人 YAMAUCHI NORIYOSHI;TANIUCHI TOSHIAKI;WADA TSUTOMU
分类号 H01L29/78;H01L21/28;H01L29/417 主分类号 H01L29/78
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