| 摘要 |
PURPOSE:To realize a high-speed signal process to a large amount of data, by carrying out a simultaneous matching of pattern to the data input by N words and forming in multiple steps the symbol pattern to be compared. CONSTITUTION:The symbol series stored in the main memory are transferred to the buffer registers BRG11a-11N by N word blocks at a time. In this instant, 1 is supplied to the latches 13a-13N in the form of the initial state, and 0 is supplied to the index registers IRG17a-17M. The pattern to be compared is put into the key pattern registers KRG18a-18M. The data given from BRG11a-11N are compared simultaneously with the symbol of KRG18a through the comparators 12a-12N to be sent to the AND circuits 14a-14N, and the signal secured with AND is put into the controller 16. An OR is secured at the controller 16, and the latches 13a-13N are set under the initial state again in the case of 0. Then the next N word is transferred to the BRG to start the process. The symbol of the KRG18b is put into the comparators 12a-12N when the OR result is 1 to be compared with the input data of the BRG. |
