| 摘要 |
PURPOSE:To realize a data transfer of N:N, by securing a synchronous control for each linkage device with the common synchronous clock partitioned by the synchronous signal and providing the right to each linkage device for a time-series use of the common parallel bus. CONSTITUTION:N pieces of linkage devices 2 are connected to the two-way logic bus 3. Each device 2 controls the cyclic stage by the stage counter 23 and with the synchronous clock produced from the synchronous clock oscillator circuit 20 of an optional device 2. The transmission request given to the own system from a computer is stored in the FF26, and the transmission request REQ signal is transmitted to the bus 3 via the FF27 and in common to each device 2 and at a stage allotted to the own system. At the same time, the clock sent from the circuit 20 is stopped by the gate 42 to establish the monopoly of the bus 3 with a transfer of data. After this, the transmission is started for the bus control synchronous clock. As a result, each device 2 can request a transfer of data to an optional device 2, thus ensuring an efficient control for the common bus and in a time-series way. |
