| 摘要 |
A programmable non-volatile semiconductor memory cell consisting of an n-channel insulated gate field effect transistor comprising a gate electrode which is floating with respect to potential, and enclosed on all sides by an insulating material and which, in its surface expansion, extends with electrode parts beyond a channel region of the insulated gate field effect transistor, which channel region is arranged on a surface of a monocrystalline semiconductor substrate, and which gate electrode is coupled capacitively by means of two electrode parts of different size via an insulated gate, to respective programming electrodes wherein an erase electrode to which an erase signal is capable of being applied, is created by a first planar zone forming a pn-junction with the semiconductor substrate and which, together with a first electrode part of the gate electrode, forms a first capacitance which is substantially smaller than a second capacitance between a second electrode part and a write electrode to which a write signal is capable of being applied, and wherein between the first planar zone and a first surface portion of said gate electrode there is arranged an insulating layer which is genetically grown on the free surface of said first planar zone and has a thickness ranging between 100 and 300 angstrom units and which forms a tunnel junction at a sufficiently high existing field strength, between said first planar zone and said first surface portion of the gate electrode so that the recharging of said gate electrode is effected by tunnel currents.
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