| 摘要 |
PURPOSE:To enable the detection of error earlier without lowering the efficiency of information processing, by reducing the period of periodic inspection accompanied with error detection and returning the period through monitor to normal period after a given time. CONSTITUTION:The timing signal T1 with a given time interval is fed to a start signal generating circuit 2 via AND gate 9 and OR gate and also fed to an address counter 1 counting the address, allowing the periodic inspection of storage device at a given period. Further, with the error signal E with the production of error, the output of a NAND circuit 7 is inverted and FF4 is set to close and open the AND gates 9, 10. Thus, the timing signal T2 shorter in the time interval than the signal T1 is used in place of the signal T1 to reduce the period of periodic inspection. On the other hand, when the maximum count value of the counter 1 is counted at a maximum address calculation circuit 3, FF4 is reset via the circuit 3 to return the period to normal one, allowing to make earlier detection and processing of error without lowering the information processing efficiency. |
